At DOEACC centre, Chennai on 29th, we completed the “Short term course on RTL modeling and verification using Verilog“. I am still surprised not many SC/ST people turned up. They could have availed fee waiver and other benefits for this 2500 rupees course.
For ten days it had been a good learning experience to dwell into digital design and implementation. To understand a new language. To learn and experience the ways in which human beings make the society better so that the world is a better place to live in.
One doesn’t expect much other than the certificate when going for such a course. There is this central government institution in a far place and only few people join p for the course. A not for profit institution has its own drawbacks. But this time it was the people who didn’t join who lost. It was a beautiful class, and fewer population means greater attention. There was freedom to ask a lot of questions, nevertheless silly it got solved. There were individual PCs to try and learn the program, constant encouragement for independent thinking. And serene ambience.
The director a friendly man asked for honest feedbacks. He said that if the course wasn’t useful then they won’t do it again. They aimed at the welfare of the youth, to make them job ready. He even encouraged us to apply for job openings in DOEACC centres are all over india,and in some places they don’t get talented trainers to conduct classes. There are good hopes to build new labs and conduct independent research in these labs.
We were told that we could approach them for any doubts at any point of time. One advantage materialised in the form of textbook on verilog primer by J Bhasker that they gave us.
Finally, there will be more happiness around if they heard from us that we landed in VLSI job of interest.